A typical memory controller requires the outgoing data (DQ) from the chip to be a quadrature phase off its data strobe (DQS) and the incoming data and data strobe needs to be offset in a similar way. A quadrature phase is equal to ¼ of a clock period. This is to ensure that the data bits (DQ) are sampled by the data strobe (DQS) in the middle of the data bits to achieve maximum setup and hold time margin. This is typically done either by using (1) a multi-phase (typically 4 phases) PLL embedded inside each data byte or (2) by using a master DLL which is periodically calibrated to generate the quadrature setting which is then conveyed to replica delay lines that are present in each byte.
In addition, due to the fly-by topology adopted by DRAM modules in DDR3, CK, commands and addresses of each SDRAM on a given DIMM card have different arrival times. The memory controller, therefore, must compensate the fly-by delay by implementing adjustable delay lines on DQS and DQ such that DQS can be aligned with its corresponding CK at any given byte. This procedure is called write leveling. Similarly for the incoming data, the memory controller also needs to stall data of different bytes with different delays so eventually all bytes can arrive at the same time with respect to the internal CK used by the memory controller; and this is called read leveling.